1. Field of the Invention
The present invention relates to a socket device for the interconnection of integrated circuits and printed circuit boards. More particularly, the present invention is an interconnection device comprising a plurality of isolated connectors, each of which provides electro-mechanical interconnection between contact pads of Integrated Circuits (ICs) and contact pads of Printed Circuit Boards (PCBs), and a removable insulative socket.
2. Description of the Prior Art
Rapid technological development in the field of semiconductors has led to ever-greater reductions in the size of integrated semiconductor circuits and, consequently, ever-greater circuit performance within a given physical area. At this point, further miniaturization is being limited by inter-circuit connection hardware. The fact is that the miniaturization of IC circuitry has not heretofore been extended in any significant way to the miniaturization of the interconnection between such circuitry. Whereas the circuit density has increased at a rapid rate, improvements focusing on increasing the number of available electro-mechanical interconnectors within the smaller physical framework has proceeded at a slower pace.
The number of fields where this "interconnection bottleneck" is and will be a problem is virtually immeasurable. In the field of Application-Specific Integrated Circuits (ASICs), for example, the interconnection problem is already an acute one. (An ASIC is any integrated circuit that is customized for a specific application, either in the field by an end user employing programmable logic, or by a semiconductor manufacturer using standard cell-based and full custom-based designs) Currently, there are ASIC chips used in cell-based designs requiring as many as 500,000 interface gates on a standard-size chip. The pin-grid-array interconnection system presently used to interconnect ICs and PCBs is capable of providing only up to about 100,000 gates for a chip of equivalent size. Even recent developments in interstitial pinning will not be able to keep up with the demand for increased contact-point density. This has led to an increased interest in leadless grid arrays in ASIC technology. This present interest in the ASIC field will soon extend to the telecommunications and computer systems fields as well. Those industries, in common with the ASIC industry, need to keep interconnection paths as short as possible in order to accommodate circuits operating at higher and higher speeds (i.e., to avoid having the overall speed limited by the leads). The current approach is to bring the signal interconnection between the circuits as close to a circuit's termination point as possible. Traditional through-board printed circuit terminals will not provide such an interconnection. Instead, a surface-mount-to-surface-mount, small-profile interconnection is required-one which will provide an interconnector which is as electrically transparent as possible. This need has also led to increasing interest in leadless grid arrays as replacements for installed pin grid arrays.
The pin density limitations noted above are attributable to, among other things, the fact that the pins themselves must provide adequate and reliable interconnection. Although it may be possible to reduce pin size to accommodate more pins for a given package size, IC industry pin requirements limit the extent to which pin diameters may be reduced. The minimum permissible pin diameter is presently 0.016". This limitation is driven by the need to provide conductive interconnectors that are of sufficient strength and rigidity to provide reliable electrical conductivity. Another factor limiting pin density is the accessibility of the pin terminal for attachment to a PCB. The process of staggering the pins for closer packing, or interstitial pinning, provides easier access to the pin terminals, but is only a temporary solution to the ever-increasing density problem. Still another factor limiting pin-grid-array density relates to the demands for contact between the pin terminals and the PCB contact points. Specifically, it is well known in the field that pin lengths may vary by as much as .+-.0.004". When large numbers of these variably-sized pins are affixed to a PCB (which itself has surface contours that magnify the problem of pin-length variations) it is extremely difficult to ensure reliable pin contact. As more and more pins become affixed, it becomes more and more difficult to join the next pin to the contact point on the PCB, particularly when the pin is a short one and the contact point is at a low spot on the PCB. Therefore, as the number of contact points on ICs and PCBs increases, the present method of interconnection of those contact points may jeopardize interconnection integrity.
As previously stated, pin grid arrays will be of limited usefulness as Input/Output (I/O) requirements--reflected in circuit gate numbers--continue to increase. In addition to the contact density limitation previously discussed, there is a limitation imposed by the process used to affix pin grid arrays to contact points on ICs and PCBs. Traditionally, there have been two basic methods for applying pin arrays, i.e., for affixing an IC to a PCB:1) soldering or brazing pin terminals onto both the IC and the PCB; 2) soldering pin terminals to the IC and inserting those pins into the PCB using socket fixtures. Several problems occur when pins are soldered or brazed to both PCB and IC contact points. Foremost of these is that once the pin grid array package is soldered to the PCB, the entire array must be removed for inspection and repair when there is a problem with one or more I/O pins located under the IC package. The time required to remove the package and repair the defect is excessive and expensive. Furthermore, the heat required to reflow the solidified solder typically causes delamination of the PCB's metalized traces from the PCB itself. If the pins are brazed on, the entire array package must be placed in an inert gas and slowly heated and then carefully cooled, also a time-consuming process requiring additional expenditures for processing materials. Complete soldering is also of concern when circuitry fails. It is generally known that most failures occur in the chips themselves. When interconnections involve soldering pins to the PCBs, the entire package must be replaced when chip failure occurs, primarily because breaking the pins from the PCBs is much too time-consuming. This last problem is partially overcome by using the other traditional method, socket fixture means. Although this eliminates half the soldering time, it does not eliminate the time needed to braze to the ICs. Furthermore, an external force must be applied to ensure adequate pin-to-PCB socket connection. Due to pin and board surface variations, and ever-increasing contact density, this force must be extremely high in order to ensure a reliable connection; it also must be sufficient to make all the interconnections gas-tight in order to prevent microcorrosion. Furthermore, when the circuitry is designed such that the pins protrude through the PCB, not only do the high-speed transfer limitations associated with through-terminal connectors arise, but the pins of these connectors must still be soldered to the PCB. Since present socketing arrangements utilize opaque plastic housing means to secure the pins in place, visual inspection of the quality of the contact between the pin and the PCB contact point is not possible. In most instances, manufacturers are required to perform x-ray inspections to evaluate contact quality, a process which is also expensive. For all of these reasons, IC and PCB developers must look to leadless grid arrays.
Leadless grid arrays simply comprise an array of conductive contact points--they are, in effect, the pin grid arrays without the pins. Elimination of the pins permits significant increases in contact-point density and eliminates all of the problems associated with pin attachment described above, and also, most of the expense. To complete the transition from pin to leadless arrays, an alternative method of interconnection between ICs and PCBs must replace the pin system described. Several methods have been developed for connecting leadless ICs with leadless PCBs. One is the two-spring contact assembly retained in an electrically-insulative socket disclosed in U.S. Pat. No. 4,838,801 issued to Bertoglio et al. in 1989. The two-element assembly of Bertoglio et al. may be used in connecting leadless arrays. The problem with this socket assembly, and others such as the one included in the mounting system described in U.S. Pat. No. 4,506,938 issued to Madden in 1985, is the impediment they present to the quality-control inspection of the interconnections. Specifically, when the springed contact assembly is affixed to the IC and PCB contact points, whether by soldering or other means, the opaque, electrically-insulative material is captured as well. In order to examine the contact quality, it is thus still necessary to perform expensive examinations, such as the x-ray evaluation previously noted for pin grid arrays. Another problem associated with contact assemblies captured in an electrically-insulative material is the fact that such materials have dielectric constants ranging from 2.5 to 4 and more. Since the contact assemblies are in contact with the material, there is no air gap. Air is an ideal insulative dielectric material; it has a dielectric constant of one. Thus an interconnection system comprising a combination of a solid insulative material and air would provide enhanced dielectric insulation qualities.
Systems which utilize small particles of conductive material dispersed within a polymeric insulative material, such as the system described in U.S. Pat. No. 4,402,562 issued to Sado in 1983, fail as highly effective interconnectors. The polymeric material, rather than the conductive element, is used to develop the electro-mechanical force necessary for reliable interconnection. Furthermore, direct contact of the insulative material and the conductive elements leads to a higher dielectric constant and, therefore, more concerns regarding spurious capacitance effects than if there was a gap between the insulative material and the conductors.
Therefore, what is needed is a low-cost interconnection system which will accommodate present and future high density leadless grid arrays of ICs and PCBs. What is also needed is an interconnection system which provides for ready access of contact elements affixable to IC and PCB contact points. Further, what is needed is an interconnection system which provides for easy means of affixing contact elements to IC and PCB contact points. Still further, what is needed is an interconnection system with reliable means for aligning contact elements with IC and PCB contact points and maintaining circuit integrity. What is also needed is an interconnection system wherein contact-element-to-contact-point integrity can be easily and inexpensively inspected.